Adata AX3U2000XB1G9-3X Datenblatt PDF herunterladen

EL67I1A08_DDR3-2000X(CL=9)_1GB(128Mx8_Pb free) Rev.0 2009/01/16 Page 2 of 7

General DescriptionΚ

ΚΚ

The ADATA’s EL67I1A08 is a 128Mx64 bits 1GB(1024MB) DDR3-2000(CL9) SDRAM XMP memory module,

The SPD is programmed to JEDEC standard latency 1333Mbps timing of 9-9-9-24 at 1.5V. The module is composed

of eight 128Mx8 bits CMOS DDR3 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TDFN package on a

240pin glass–epoxy printed circuit board.

The EL67I1A08 is a Dual In-line Memory Module and intended for mounting onto 240-pins edge connector

sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are

possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow

the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FeaturesΚ

ΚΚ

• Power supply (Normal): VDD & VDDQ = 1.5V ± 0.075V

• 1.5V (SSTL_15 compatible) I/O

• XMP (Extreme Memory Profile) support

• Timing Reference

- DDR3 1333 CL9-9-9-24 at 1.5V

- DDR3 2000 CL9-9-9-24 at 2.05V (XMP Profile 1)

• Burst Length: 4, 8

• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock

• Bi-directional, differential data strobe (DQS and /DQS)

• Differential clock input (CK, /CK) operation

• DLL aligns DQ and DQS transition with CK transition

• Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C

• 8-bit pre-fetch.

• On Die Termination using ODT pin

• Internal (self) calibration: Internal self calibration through ZQ pin (RZQ: 240 ohm ± 1%)

• EEPROM VDDSPD=3.3V (Typical)

• PCB Height 30.00mm (1.181”), Single sided component

• Clock Cycle Time (tCK):

- DDR3-1333 tCK=1.5ns

- DDR3-2000 tCK=1.0ns

• Refresh to Active/Refresh Command Time (tRFC): 110ns

• Lead-free products are RoHS compliant

DDR3-2000X(CL9) 240-Pin XMP U-DIMM

1GB (128M x 64-bits)

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